1. Field of the Invention
The invention relates generally to methods for forming conductive structures on substrates. In particular, the invention relates methods that involve conductive structures of fine resolution formed using non-subtractive, printing, particulate deposition and/or bonding techniques.
2. Description of Background Art
Lithographic techniques are commonly used in the semiconductor industry and the microelectromechanical systems (MEMS) industry for fabricating devices. For example, front end semiconductor fabrication processes may use photolithographic techniques designed to image substrates via a coat-expose-remove process to form a desired pattern, e.g., a microelectronic circuit, on the substrate surface. Such techniques typically involve a substractive deposition procedure in which the entire substrate surface is coated with a photoresist, the photoresist is exposed to an image, and the photoresist is developed in a manner that results in the selective removal of photoresist from the substrate surface. As a result, the photoresist forms a pattern that corresponds to the image. The remaining resist may serve as a mold in which material may be deposited.
Moore's Law describes a historical trend in the microelectronic and semiconductor industry, which holds that the number of transistors per unit area that can be included on a silicon-based integrated circuit doubles about every two years. Since this observation was described in a 1965 paper, the trend has continued for more than half a century. Persons of ordinary skill in the art recognize that almost every measure of the capabilities of digital electronic devices is linked to Moore's Law. Improvements in lithographic technology are seen as a driver for advancing Moore's law in the quest to produce smaller and smaller transistors, thereby resulting in improved device performance at a lower cost.
Recently, photolithographic technology has found greater utilization in back-end semiconductor fabrication processes, e.g., those involving semiconductor packaging. Previously, advanced semiconductor packaging has generally involved wire-bonding individual dies formed from semiconductor wafers. More recently, however, photolithographic techniques have been used to pattern wafer-level interconnects. Similarly, photolithographic techniques have been proposed for use with reconstituted substrates.
In particular, photolithographic technologies have been used in microelectronic packaging applications to define an electroplating mold in which metal is electroplated. Once the mold is removed, the electroplated metal may serve as conductive interconnects.
Typically, photolithographic techniques in the context microelectronic packaging applications involve several steps. First, a wafer containing microelectronic devices is spin coated with photoresist. Then the wafer is baked to drive out solvents in the resist, and exposed lithographically using a photolithography tool and a master pattern, e.g., a mask or reticle. Once exposed, the resist is developed and baked again to enhance its stability. The wafer's surface is then cleaned to remove any residual contaminants. Once the surface has been cleaned, metal is electroplated thereon. Finally, resist is stripped from the wafer, leaving the metal to serve as conductive interconnects.
In practice, the above-described example requires a track containing numerous expensive and complex tools in a manufacturing line. For example, the line requires a resist dispenser/spin coater to spread the photoresist uniformly on the wafer. After the wafer is coated, the wafer is transferred to a heating station followed by a lithography tool. Once exposed, the wafer is passed on to developer and post-exposure heating stations. Then, the wafer is passed on to a plasma ashing station for cleaning. After plating has occurred in an electroplating bath, the remaining resist is removed using a strip tool.
The above-described photolithography-based electroplating sequence is generally considered a complex process in the context of microelectronic packaging applications. Other microelectronic packaging applications of a similar level of complexity include, for example, those involving solder-bumping, redistribution layers, and reconstituted substrates with associated devices. In addition, numerous microelectronic packaging applications involve the use of a reticle for exposure during a lithography step. Depending upon the linewidths, pattern complexity and wafer volume, reticle costs per wafer can be significant.
As process simplification tends to reduce process cost and improve process reliability, there is an unmet need for improved technologies whose performance meets that of photolithographic technologies for microelectronic applications without the drawbacks associated with photolithography.